FPGA Technology at Crossroads

Field Programmable Gate Arrays (FPGAs) have been undergoing rapid and dramatic changes fueled by their expanding use in datacenter computing. Rather than serving as a compromise or alternative to ASICs, FPGA ‘programmable logic’ is emerging as a third paradigm of compute that stands apart from traditional hardware vs. software archetypes. A multi-university, multi-disciplinary team has been formed behind the question:

What should be the future role of FPGAs as a central function in datacenter servers?

Guided by both the demands of modern networked, data-centric computing and the new capabilities from 3D integration, the Intel/VMware Crossroads 3D-FPGA Academic Research Center will investigate a new programmable hardware data-nexus lying at the heart of the server and operating over data ‘on the move’ between network, traditional compute, and storage elements.

The Intel/VMware Crossroads 3D-FPGA Academic Research Center is jointly supported by Intel and VMware. The center is committed to public and free dissemination of its research outcome.

You can find an overview presentation on the center’s YouTube channel. Please contact any of the Crossroads PIs in your research area if you have any questions or interest.


Latest News

May 18, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center launches a YouTube Channel for its seminar series.


April 23, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center launches its seminar series with Joe Melber as the inaugural speaker presenting his PhD dissertation work on a service-oriented memory abstraction and infrastructure for computing FPGAs.


April 2021 | Mohamed Ibrahim and Andrew Boutros collaborated with Anupreetham of Arizona State University, and Eriko Nurvitadhi of Intel to develop a higher performance architecture for single shot object detection (SSD) using FPGAs. The architecture combines the HPIPE CNN architecture that uses customized hardware for each layer of a CNN to achieve high performance with a new, FPGA-friendly non-maximum suppression (NMS) technique to remove overlapping object bounding boxes. Please contact Andrew Boutros, Mohamed Ibrahim and Vaughn Betz (University of Toronto).


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Recent Publications

  • We Need Kernel Interposition over the Network Dataplane [abstract] [paper]

    Sadok, H., Zhao, Z., Choung, V., Atre, N., Berger, D. S., Hoe, J. C., Panda, A., & Sherry, J. (2021). We Need Kernel Interposition over the Network Dataplane. In Proceedings of the Workshop on Hot Topics in Operating Systems. Ann Arbor, MI, USA. ACM, New York, NY, USA. ACM, New York, NY, USA. [bibtex]

    Abstract:
    Kernel-bypass networking, which allows applications to circumvent the kernel and interface directly with NIC hardware, is one of the main tools for improving application network performance. However, allowing applications to circumvent the kernel makes it impossible to use tools (e.g., tcpdump) or impose policies (e.g., QoS and filters) that need to interpose on traffic sent by different applications running on a host. This makes maintainability and manageability a challenge for kernel-bypass applications. In response, we propose Kernel On-Path Interposition (KOPI), in which traditional kernel dataplane functionality is retained but implemented in a fully programmable SmartNIC. We hypothesize that KOPI can support the same tools and policies as the kernel stack while retaining the performance benefits of kernel bypass.
    BibTeX:
    @inproceedings{Sadok2021,
    author = {Sadok, Hugo and Zhao, Zhipeng and Choung, Valerie and Atre, Nirav and Berger, Daniel S. and Hoe, James C. and Panda, Aurojit and Sherry, Justine},
    title = {We Need Kernel Interposition over the Network Dataplane},
    year = {2021},
    isbn = {},
    publisher = {Association for Computing Machinery},
    address = {New York, NY, USA},
    booktitle = {Proceedings of the Workshop on Hot Topics in Operating Systems},
    pages = {1–6},
    numpages = {6},
    month = jun,
    series = {{HotOS}~'21}
    }
    
  • Achieving 100Gbps Intrusion Prevention on a Single Server [abstract] [paper] [slides] [video] [code]

    Zhao, Z., Sadok, H., Atre, N., Hoe, J., Sekar, V., & Sherry, J. (2020). Achieving 100Gbps Intrusion Prevention on a Single Server. In Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI). Berkeley, CA, USA: USENIX Association. [bibtex]

    Abstract:
    Pigasus is an 100Gbps Intrusion Detection and Prevention System that can inspect network traffic by checking against 10K+ rules with the support of 100K+ concurrent connections. Pigasus is implemented on a single server using one FPGA-based SmartNIC with a few CPU cores, saving hundreds of cores compared with CPU-only approach. The Github repository contains the FPGA RTL code, CPU full matcher code and scripts for RTL simulation, synthesis build and hardware onboard test.
    BibTeX:
    @inproceedings {258923,
    author = {Zhipeng Zhao and Hugo Sadok and Nirav Atre and James C. Hoe and Vyas Sekar and Justine Sherry},
    title = {Achieving 100Gbps Intrusion Prevention on a Single Server},
    booktitle = {14th {USENIX} Symposium on Operating Systems Design and Implementation ({OSDI} 20)},
    year = {2020},
    isbn = {978-1-939133-19-9},
    pages = {1083--1100},
    url = {https://www.usenix.org/conference/osdi20/presentation/zhao-zhipeng},
    publisher = {{USENIX} Association},
    month = nov,
    }
    

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